Top-side connector interface for processor packaging

ABSTRACT

An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.

CLAIM OF PRIORITY

The present application is a Continuation of and claims priority to U.S.patent application Ser. No. 15/172,102, filed Jun. 2, 2016 and titled“TOP-SIDE CONNECTOR INTERFACE FOR PROCESSOR PACKAGING,” which isincorporated by reference in its entirety.

CROSS REFERENCE TO RELATED APPLICATION

The present application is related to U.S. application Ser. No.14/975,941 (Attorney Docket No. P90147), titled “WARPAGE MITIGATION INPRINTED CIRCUIT BOARD ASSEMBLIES,” filed Dec. 21, 2015, which isincorporated by reference in its entirety.

BACKGROUND

Accessing signals from an integrated circuit generally involves routingthe signals through a processor substrate, package, motherboard, etc.,and then to interfaces on the motherboard. Connectors can also be usedto interface with the motherboard to access the signal routes. However,connectors are bulky and present a challenge to interface with theintegrated circuit directly.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the disclosure will be understood more fully from thedetailed description given below and from the accompanying drawings ofvarious embodiments of the disclosure, which, however, should not betaken to limit the disclosure to the specific embodiments, but are forexplanation and understanding only.

FIG. 1 illustrates a cross-sectional view of a packaging system with aLinear Edge Connector (LEC) for accessing signals from a processorsubstrate coupled to a Land Grid Array (LGA) socket.

FIG. 2 illustrates a cross-sectional view of a packaging system with aninterposer having an extended region to couple to top-side connector,according to some embodiments of the disclosure.

FIG. 3 illustrates a perspective view of the packaging system of FIG. 2,according to some embodiments of the disclosure.

FIG. 4 illustrates a cross-sectional view of a packaging system with aprocessor substrate having an extended region to couple to a top-sideconnector, according to some embodiments of the disclosure.

FIG. 5 illustrates a perspective view of the packaging system of FIG. 4,according to some embodiments of the disclosure.

FIG. 6 illustrates a cross-sectional view of an integrated circuit (IC)package assembly which is configured to be coupled to a top-sideconnector, in accordance with various embodiments.

FIG. 7 illustrates a cross-sectional view of a socket packaging systemwith a processor substrate having an extended region to couple to atop-side connector, according to some embodiments of the disclosure.

FIG. 8 illustrates a perspective view of the packaging system of FIG. 7,according to some embodiments of the disclosure.

FIG. 9 illustrates a flowchart of a method of forming the packagesystem, in accordance with some embodiments.

FIG. 10 illustrates a smart device or a computer system or a SoC(System-on-Chip) which is packaged and connectable to a top-sideconnector, according to some embodiments.

DETAILED DESCRIPTION

Land grid array (LGA) is a type of packaging for integrated circuits(ICs). LGA sockets have a solder ball on one side of the socket that isattached to a cantilever contact. The cantilever contact is theinterface point to the LGA package. The LGA package has an array ofconductive pads that the LGA socket cantilever contact makes electricalcontact with. FIG. 1 illustrates cross-sectional view 100 of a packagingsystem with a Linear Edge Connector (LEC) for accessing signals from aprocessor substrate coupled to an LGA socket. The packaging system ofFIG. 1 comprises motherboard 101, array of contacts 102, LGA socket 103,CPU (central processing unit, or any processor) substrate 104, CPU die105, LEC connector 106, and fabric interconnect cable 107. The array ofcontacts 102 may be ball grid array (BGA) balls that make contactbetween LGA Socket 103 and motherboard 101 (e.g., printed circuit boardPCB)). A person skilled in the art would appreciate that other detailssuch as cantilever contacts interfacing with the CPU Substrate 104 arenot shown, but are present. Here, LEC 106 couples to CPU substrate 104to provide access to signal routing from CPU die 105. These signalroutings may also be extending towards motherboard 101 (e.g., PCB) viaLGA Socket 103. LGA Socket 103 separates CPU die 105 from motherboard101 by a height ‘h’ which is high enough for allowing LEC 106 to couplewith an extended region of CPU substrate 104.

As computing platforms scale in size and computing devices becomesmaller in form factor, LGA sockets for their bulky nature become lessattractive as a design choice. Computing platforms that are movingtowards thinner packaging technologies such as Ball Grid Array (BGA)packaging, which is generally thinner than LGA socket 103, cannot useLEC 106 to communicatively couple to CPU substrate 104 because thethinner BGA packaging results in lower ‘h’ than the ‘h’ shown in FIG. 1.As such, connectors such as LEC 106 cannot access signal routings on CPUsubstrate 104 because there is not enough clearance for LEC 106 tocouple to CPU substrate 104.

Some embodiments provide an electro-mechanical interface between atop-side connector and a processor package (e.g., BGA package). In someembodiments, an apparatus is provided which comprises a processorsubstrate having a region extended away from a processor die, where theprocessor die is mounted on the processor substrate, and where theextended region has at least one signal interface which is connectableto a top-side connector. In some embodiments, an apparatus is providedwhich comprises an interposer coupled to the processor substrate and amotherboard, where the interposer has a region which is extended awayfrom the processor substrate, where the extended region of theinterposer has at least one signal path communicatively coupled to theprocessor die, and where the extended region of the interposer isconnectable to a top-side connector. The various embodiments allow oneor more top-side connectors to provide an access to processor signalroutings. Other technical effects will be evident from the variousembodiments and figures.

In the following description, numerous details are discussed to providea more thorough explanation of embodiments of the present disclosure. Itwill be apparent, however, to one skilled in the art, that embodimentsof the present disclosure may be practiced without these specificdetails. In other instances, well-known structures and devices are shownin block diagram form, rather than in detail, in order to avoidobscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals arerepresented with lines. Some lines may be thicker, to indicate moreconstituent signal paths, and/or have arrows at one or more ends, toindicate primary information flow direction. Such indications are notintended to be limiting. Rather, the lines are used in connection withone or more exemplary embodiments to facilitate easier understanding ofa circuit or a logical unit. Any represented signal, as dictated bydesign needs or preferences, may actually comprise one or more signalsthat may travel in either direction and may be implemented with anysuitable type of signal scheme.

Throughout the specification, and in the claims, the term “connected”means a direct connection, such as electrical, mechanical, or magneticconnection between the things that are connected, without anyintermediary devices. The term “coupled” means a direct or indirectconnection, such as a direct electrical, mechanical, or magneticconnection between the things that are connected or an indirectconnection, through one or more passive or active intermediary devices.The term “circuit” or “module” may refer to one or more passive and/oractive components that are arranged to cooperate with one another toprovide a desired function. The term “signal” may refer to at least onecurrent signal, voltage signal, magnetic signal, or data/clock signal.The meaning of “a,” “an,” and “the” include plural references. Themeaning of “in” includes “in” and “on.”

The term “scaling” generally refers to converting a design (schematicand layout) from one process technology to another process technologyand subsequently being reduced in layout area. The term “scaling”generally also refers to downsizing layout and devices within the sametechnology node. The term “scaling” may also refer to adjusting (e.g.,slowing down or speeding up—i.e. scaling down, or scaling uprespectively) of a signal frequency relative to another parameter, forexample, power supply level. The terms “substantially,” “close,”“approximately,” “near,” and “about,” generally refer to being within+/±10% of a target value.

Unless otherwise specified the use of the ordinal adjectives “first,”“second,” and “third,” etc., to describe a common object, merelyindicate that different instances of like objects are being referred to,and are not intended to imply that the objects so described must be in agiven sequence, either temporally, spatially, in ranking or in any othermanner.

For the purposes of the present disclosure, phrases “A and/or B” and “Aor B” mean (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B and C). The terms “left,” “right,”“front,” “back,” “top,” “bottom,” “over,” “under,” and the like in thedescription and in the claims, if any, are used for descriptive purposesand not necessarily for describing permanent relative positions.

FIG. 2 illustrates cross-sectional view 200 of a packaging system withan interposer having an extended region to couple to a top-sideconnector, according to some embodiments of the disclosure. It ispointed out that those elements of FIG. 2 having the same referencenumbers (or names) as the elements of any other figure can operate orfunction in any manner similar to that described, but are not limited tosuch.

Packaging system 200 of FIG. 2 comprises motherboard 101 (e.g., PCB),interposer 201, interposer-to-PCB contacts 202 (e.g., solder balls),interposer-to-substrate contacts 203 (e.g., solder balls), CPU substrate104, CPU die 105, and top-side connector 224. While the variousembodiments here are illustrated with reference to a CPU being theprocessor die, any processor or integrated circuit die can be usedinstead of CPU die 105. For example, the processor die may be a digitalsignal processor die, a radio frequency integrated circuit die, etc.

In some embodiments, interposer 201 has an extended region 221 a whichis extended away from CPU substrate 104. In some embodiments, theextended region 221 a of interposer 201 has at least one signal pathcommunicatively coupled to CPU die 105. In some embodiments, theextended region 221 a of interposer 201 is connectable to a top-sideconnector 224. In some embodiments, top-side connector has a region 225a which is used to couple top-side connector 224 to the extended region221 a via fasteners 226 a (e.g., screws). In some embodiments, top-sideconnector 224 is a male part which connects to a corresponding femalepart (e.g., a flexible interconnect fabric). In some embodiments,top-side connector 224 is a female part which connects to acorresponding male part (e.g., a flexible interconnect fabric). Top-sideconnector 224 can access processor signal routings directly instead ofaccessing them via motherboard 101, in accordance with some embodiments.As such, top-side connector 224 of various embodiments can be used foraccessing high-speed input-output (HSIO) signals because delay path forthese signals is shortened via top-side connector 224.

In some embodiments, interposer 201 provides the routing between CPUsubstrate 104 and motherboard 101. For example, interposer 201 widensthe pitch of contacts 203 to a wider pitch of contacts 202 to rerouteconnections from CPU substrate 104 to a different connection. In someembodiments, interposer 201 is a Reflow Grid Array (RGA) which hasembedded heaters. In some embodiments, RGA allows the BGA package to bereflowed to interposer 201. RGA of various embodiments can also be usedto control warpage and monitor temperature of the RGA.

Thermal mismatch between materials used in a motherboard can causedeformation of the motherboard, resulting in stress to solder joints andcomplications during manufacturing and assembly (e.g., during packageand component attach phases). Conventionally, mechanical frames andclamps are used to prevent warping in some motherboards. The embeddedheaters in interposer 201 can provide local heat to reflow to solderballs 203, and as such mitigate the warping of motherboard 101, inaccordance with some embodiments. In some embodiments, heater traces areprovided within motherboard 101 to selectively heat portions ofmotherboard 101 to maintain a uniform temperature profile acrossmotherboard 101. This uniform temperature profile may result in uniformthermal expansion of motherboard 101. As such, warpage risk and degreeis reduced.

In some embodiments, interposer 201 may also include one or more heatertraces and/or temperature sensors to monitor the heat reflow throughinterposer 201. In some embodiments, different layers in interposer 201including heater traces and/or traces for temperature sensors are spacedapart by insulator layers (e.g., formed of dielectric material). Theinsulator layers may include vias to electrically couple different metallayers. In some embodiment, interposer 201 may include one or more metalplanes that may act as heat spreaders and may assist in achieving auniform temperature profile across interposer 201. The variousembodiments described here are not limited to RGA for interposer 201. Insome embodiments, interposers without embedded heaters can be used.

Interposer 201 of the various embodiments may be formed of a variety ofmaterials. For example, interposer 201 may be formed of an epoxy resin,a fiberglass-reinforced epoxy resin, a ceramic material, or a polymermaterial such as polyimide. In some embodiments, interposer 201 may beformed of alternate rigid or flexible materials, such as silicon,germanium, and other group III-V and group IV materials of the PeriodicTable. In some embodiments, interposer 201 may include metalinterconnects and vias including but not limited to through-silicon vias(TSVs). In some embodiments, interposer 201 may include embedded devicesincluding both passive and active devices. Such devices may include, butare not limited to, capacitors, decoupling capacitors, resistors,inductors, fuses, diodes, transformers, sensors, electrostatic discharge(ESD) devices, and memory devices. In some embodiments, interposer 201may include complex devices such as radio-frequency (RF) devices, poweramplifiers, power management devices, antennas, arrays, sensors, andmicroelectromechanical systems (MEMS) devices, etc.

In some embodiments, CPU substrate 104 is a multi-layer substrate withsignal, power, and ground routings distributed in various layers. Insome embodiments, these signal, power, and ground routings pass throughinterposer 201 and are also accessible to top-side connector 224. Anyknown suitable material can be used for forming CPU substrate 104.

FIG. 3 illustrates perspective view 300 of the packaging system of FIG.2, according to some embodiments of the disclosure. It is pointed outthat those elements of FIG. 3 having the same reference numbers (ornames) as the elements of any other figure can operate or function inany manner similar to that described, but are not limited to such.

Perspective view 300 illustrates top-side connector 224 having twoconnection regions 320 a and 320 b, respectively. These connectionregions have connectors 325 a and 325 b which are used to couple toanother device (e.g., a flexible interconnect fabric). In someembodiments, both connectors 325 a and 325 b are male connectors. Insome embodiments, both connectors 325 a and 325 b are female connectors.In some embodiments, one of the connectors (e.g., 325 a) is a femaleconnector and the other connector (e.g., 325 b) is male connector. Theseconnectors are electrically connected to signal routings from CPU die105 via CPU substrate 104 and interposer 201. In some embodiments,top-side connector 224 is fastened to the extended region 221 a ofinterposer 201 via fasteners (e.g., screws) 226 a and 226 b which areinsert-able in their respective regions 225 a and 225 b. Whileperspective view 300 illustrates one top-side connector 224 coupling toone side of interposer 201, top-side connectors can be coupled to othersides of interposer 201. For example, the packing system may includeextended interposer regions along the north, west, and/or south sides ofinterposer 201, and these extended regions may couple to theirrespective connectors.

FIG. 4 illustrates cross-sectional view 400 of a packaging system with aprocessor substrate having an extended region to couple to a top-sideconnector, according to some embodiments of the disclosure. It ispointed out that those elements of FIG. 4 having the same referencenumbers (or names) as the elements of any other figure can operate orfunction in any manner similar to that described, but are not limited tosuch.

In some embodiments, CPU substrate 104 is elongated along the directionof motherboard 101 and top-side connector 224 to mechanically couplewith it. The extended region of CPU substrate 104 is region 104 a. Insome embodiments, CPU substrate 104 is a multi-layer substrate withsignal, power, and ground routings distributed in various layers. Insome embodiments, these signal, power, and ground routings pass throughinterposer 201 and are also accessible by top-side connector 224. Anyknown suitable material can be used for forming CPU substrate 104. Insome embodiments, interposer 201 is extended at least as much as theextended CPU substrate 104 to provide mechanical strength to theextended region 104 a of CPU substrate 104. The extended region ofinterposer 201 is 221. In some embodiments, top-side connector 224 has aregion 225 a which is used to couple top-side connector 224 to theextended region 104 a via fasteners 226 a (e.g., screws). In someembodiments, top-side connector 224 is a male part which connects to acorresponding female part (e.g., a flexible interconnect fabric). Insome embodiments, top-side connector 224 is a female part which connectsto a corresponding male part (e.g., a flexible interconnect fabric).

FIG. 5 illustrates perspective view 500 of the packaging system of FIG.4, according to some embodiments of the disclosure. It is pointed outthat those elements of FIG. 5 having the same reference numbers (ornames) as the elements of any other figure can operate or function inany manner similar to that described, but are not limited to such.

Perspective view 500 illustrates top-side connector 224 having twoconnection regions 320 a and 320 b, respectively, which attach toextended CPU substrate region 104 a. These connection regions haveconnectors 325 a and 325 b which are used to couple to another device(e.g., a flexible interconnect fabric). In some embodiments, bothconnectors 325 a and 325 b are male connectors. In some embodiments,both connectors 325 a and 325 b are female connectors. In someembodiments, one of the connectors (e.g., 325 a) is a female connectorand the other connector (e.g., 325 b) is male connector. Theseconnectors are electrically connected to signal routings from CPU die105 via CPU substrate 104 and extended region 104 a. In someembodiments, connector 225 is fastened to the extended region 104 a ofCPU substrate 104 via fasteners (e.g., screws) 226 a and 226 b which areinsert-able in their respective regions 225 a and 225 b. Whileperspective view 500 illustrates one top-side connector 224 coupling toone side of CPU substrate 104, top-side connectors can be coupled toother sides of CPU substrate 104. For example, the packing system mayinclude extended substrate regions along the north, west, and/or southsides of CPU substrate 104, and these extended regions may couple totheir respective connectors.

FIG. 6 illustrates cross-sectional view 600 of an integrated circuit(IC) package assembly which is configured to be coupled to a top-sideconnector, in accordance with various embodiments. It is pointed outthat those elements of FIG. 6 having the same reference numbers (ornames) as the elements of any other figure can operate or function inany manner similar to that described, but are not limited to such.

In some embodiments, IC package assembly may include First die 601,package substrate 604/104, interposer 201 (and 221), and circuit board622/101. IC package assembly of cross-sectional view 600 is one exampleof a stacked die configuration in which First die 601 is coupled topackage substrate 604/104, and Second die 602 is coupled with First die601, in accordance with some embodiments.

In some embodiments, First die 601 may have a first side S1 and a secondside S2 opposite to the first side SI. In some embodiments, the firstside SI may be the side of the die commonly referred to as the“inactive” or “back” side of the die. In some embodiments, the secondside S2 may include one or more transistors, and may be the side of thedie commonly referred to as the “active” or “front” side of the die. Insome embodiments, second side S2 of First die 601 may include one ormore electrical routing features 606. In sonic embodiments, second die602 may include an “active” or “front” side with one or more electricalrouting features 606. In some embodiments, electrical routing features606 may be bond pads (e.g., formed from a combination of bumps 602 a andsolder balls 603 a).

In some embodiments, Second die 602 may be coupled to First die 601 in afront-to-back configuration (e.g., the “front” or “active” side ofSecond die 602 is coupled to the “back” or “inactive” side S1 of Firstdie 601). In some embodiments, dies may be coupled with one another in afront-to-front, back-to-back, or side-to-side arrangement. In someembodiments, one or more additional dies may be coupled with First die601, Second die 602, and/or with package substrate 604/104. Otherembodiments may lack Second die 602. In some embodiments, First die 601may include one or more TSVs. In some embodiments, Second die 602 iscoupled to First die 601 by die interconnects formed from combination ofbumps and solder balls 603. In some embodiments, solder balls 603 areformed using the solder-on-die (SOD) process.

In some embodiments, inter-die interconnects may be solder bumps, copperpillars, or other electrically conductive features. In some embodiments,an interface layer 624 may be provided between First die 601 and Seconddie 602. In some embodiments, interface layer 624 may be, or mayinclude, a layer of under-fill, adhesive, dielectric, or other material.In some embodiments, interface layer 624 may serve various functions,such as providing mechanical strength, conductivity, heat dissipation,or adhesion.

In some embodiments, First die 601 and Second die 602 may be single dies(e.g., First die 601 is a single die instead of multiple dies). In otherembodiments, First die 601 and/or Second die 602 may include two or moredies. For example, in some embodiments First die 601 and/or Second die602 may be a wafer (or portion of a wafer) having two or more diesformed on it. In some embodiments, First die 601 and/or Second die 602includes two or more dies embedded in an encapsulant. In someembodiments, the two or more dies are arranged side-by-side, verticallystacked, or positioned in any other suitable arrangement. In someembodiments, the IC package assembly may include, for example,combinations of flip-chip and wire-bonding techniques, interposers,multi-chip package configurations including system-on-chip (SoC) and/orpackage-on-package (PoP) configurations to route electrical signals.

In some embodiments, First die 601 and/or Second die 602 may be aprimary logic die. In some embodiments, First die 601 and/or Second die602 may be configured to function as memory, an application specificcircuit (ASIC), a processor, or some combination of such functions. Forexample, First die 601 may include a processor and Second die 602 mayinclude memory. In some embodiments, one or both of First die 601 andSecond die 602 may be embedded in encapsulant 608. In some embodiments,encapsulant 608 can be any suitable material, such as an Ajinomoto Film(ABF) substrate, other dielectric/organic materials, resins, epoxies,polymer adhesives, silicones, acrylics, polyimides, cyanate esters,thermoplastics, and/or thermosets.

In some embodiments, First die 601 may be coupled to package substrate604/104 (e.g., CPU substrate). In some embodiments, package substrate604 may be a coreless substrate. For example, package substrate 604 maybe a bumpless build-up layer (BBUL) assembly that includes a pluralityof “bumpless” build-up layers. Here, the term “bumpless build-up layers”generally refers to layers of substrate and components embedded thereinwithout the use of solder or other attaching means that may beconsidered “bumps.”

In some embodiments, the one or more build-up layers may have materialproperties that may be altered and/or optimized for reliability, warpagereduction, etc. In some embodiments, package substrate 604/104 may becomposed of a polymer, ceramic, glass, or semiconductor material. Insome embodiments, package substrate 604/104 may be a conventional coredsubstrate and/or an interposer.

In some embodiments, interposer 201/221 is provided between circuitboard 622 and substrate 604. Interposer 201/221 of the variousembodiments may be formed of a variety of materials. For example,interposer 201/221 may be formed of an epoxy resin, afiberglass-reinforced epoxy resin, a ceramic material, or a polymermaterial such as polyimide. In some embodiments, interposer 201/221 maybe formed of alternate rigid or flexible materials, such as silicon,germanium, and other group III-V and group IV materials of the PeriodicTable. In some embodiments, interposer 201/221 may include metalinterconnects and vias including but not limited to TSVs. In someembodiments, interposer 201 may include embedded devices including bothpassive and active devices. Such devices may include, but are notlimited to, capacitors, decoupling capacitors, resistors, inductors,fuses, diodes, transformers, sensors, ESD devices, and memory devices.In some embodiments, interposer 201/221 may include complex devices suchas RF devices, power amplifiers, power management devices, antennas,arrays, sensors, and MEMS devices, etc. In some embodiments, packageinterconnects 612 a/203 may couple electrical routing features 610 adisposed on the second side of package substrate 604 to correspondingelectrical routing features 616 a on interposer 201.

In some embodiments, circuit board (or motherboard) 622/101 may be a PCBcomposed of an electrically insulative material such as an epoxylaminate. For example, circuit board 622 may include electricallyinsulating layers composed of materials such as, for example,polytetrafluoroethylene, phenolic cotton paper materials such as FlameRetardant 4 (FR-4), FR- 1, cotton paper and epoxy materials such asCEM-1 or CEM-3, or woven glass materials that are laminated togetherusing an epoxy resin prepreg material.

Structures such as traces, trenches, and vias (which are not shown here)may be formed through the electrically insulating layers to route theelectrical signals of First die 601 through the circuit board 622.Circuit board 622 may be composed of other suitable materials in otherembodiments. In some embodiments, circuit board 622 may include otherelectrical devices coupled to the circuit board that are configured toroute electrical signals to or from First die 601 through circuit board622. In some embodiments, circuit board 622 may be a motherboard.

In some embodiments, a one side of interposer 201/221 is coupled to thesecond side of substrate 604/104 via routings 616 a, 612 a, and 610 a.In some embodiments, another side of interposer 201/221 is coupled tocircuit board 622 by package interconnects 610 b, 612 b/102, and 616 b.

In some embodiments, package substrate 604 may have electrical routingfeatures formed therein to route electrical signals between First die601 (and/or the Second die 602) and circuit board 622 and/or otherelectrical components external to the IC package assembly. For example,electrical routing features pass through extended section 104 a totop-side connector 224. In some embodiments, package interconnects 612a/b and die interconnects 606 include any of a wide variety of suitablestructures and/or materials including, for example, humps, pillars orballs formed using metals, alloys, solderable material, or theircombinations. In some embodiments, electrical routing features 610 maybe arranged in a ball grid array (“BGA”) or other configuration. In someembodiments, substrate 604/104 has an extended region 104 a to holdtop-side connector 224. In some embodiments, interposer 201 has anextended region 221 to provide support for the extended substrate region104 a. In some embodiments, package interconnect and contacts 612 a/203and 610 a are also placed under the extended region 104 a to providemechanical support to the extended region 104 a. In some embodiments,top-side connector 224 is coupled to the extended region 104 a.

FIG. 7 illustrates cross-sectional view 700 of a socket packaging systemwith a processor substrate having an extended region to couple totop-side connector, according to some embodiments of the disclosure. Itis pointed out that those elements of FIG. 7 having the same referencenumbers (or names) as the elements of any other figure can operate orfunction in any manner similar to that described, but are not limited tosuch. In some embodiments, instead of an LEC connector 106 of FIG. 1,top-side connector may be desired. In one such embodiment, top-sideconnector 224 is fastened on the extended region 104 a of CPU substrate104. The remaining figure is similar to FIG. 1.

FIG. 8 illustrates perspective view 800 of the packaging system of FIG.7, according to some embodiments of the disclosure. It is pointed outthat those elements of FIG. 8 having the same reference numbers (ornames) as the elements of any other figure can operate or function inany manner similar to that described, but are not limited to such.

Perspective view 800 illustrates top-side connector 224 having twoconnection regions 320 a and 320 b, respectively, which attach toextended CPU substrate region 104 a. These connection regions haveconnectors 325 a and 325 b which are used to couple to another device(e.g., a flexible interconnect fabric). Here, CPU substrate 104 couplesto motherboard 101 via socket 103 (e.g., LGA socket). In someembodiments, both connectors 325 a and 325 b are male connectors. Insome embodiments, both connectors 325 a and 325 b are female connectors.In some embodiments, one of the connectors (e.g., 325 a) is a femaleconnector and the other connector (e.g., 325 b) is male connector. Theseconnectors are electrically connected to signal routings from CPU die105 via CPU substrate 104 and extended region 104 a. In someembodiments, connector 225 is fastened to the extended region 104 a ofCPU substrate 104 via fasteners (e.g., screws) 226 a and 226 b which areinsert-able in their respective regions 225 a and 225 b. Whileperspective view 800 illustrates one top-side connector 224 coupling toone side of CPU substrate 104, top-side connectors can be coupled toother sides of CPU substrate 104. For example, the packing system mayinclude extended substrate regions along the north, west, and/or southsides of CPU substrate 104, and these extended regions may couple totheir respective connectors.

The various embodiments described here are not limited to any one kindof packing technology. The top-side connector of various embodiments canbe coupled to any processor package (e.g., ball grid array (BGA)package, pin grid array (PGA), flip-chip PGA (FCPGA), staggered PGA(SPGA), ceramic PGA (CPGA), organic PGA (OPGA), stud grid arrau (SGA),reduced PGA (rPGA), LGA, etc.).

FIG. 9 illustrates flowchart 900 of a method of forming the packagesystem, in accordance with some embodiments. It is pointed out thatthose elements of FIG. 9 having the same reference numbers (or names) asthe elements of any other figure can operate or function in any mannersimilar to that described, but are not limited to such. Although theblocks in the flowchart with reference to FIG. 9 are shown in aparticular order, the order of the actions can be modified. Thus, theillustrated embodiments can be performed in a different order, and someactions/blocks may be performed in parallel. Some of the blocks and/oroperations listed in FIG. 9 are optional in accordance with certainembodiments. The numbering of the blocks presented is for the sake ofclarity and is not intended to prescribe an order of operations in whichthe various blocks must occur. Additionally, operations from the variousflows may be utilized in a variety of combinations.

At block 901, processor die 105 is mounted on processor substrate layer104. At block 902, processor substrate 104 is mounted to interposer 201.Here, interposer has a region 221 a which is extended away fromprocessor substrate 104, where extended region 221 a of interposer 201has at least one signal path communicatively coupled to processor die105, and where extended region 221 a of interposer 221 is connectable totop-side connector 224. At block 903, top-side connector 224 is coupledto extended region 221 a of the interposer 201. At block 904, top-sideconnector 224 is fastened to extended region 221 a via at least twoscrews 226 a and 226 b.

FIG. 10 illustrates a smart device or a computer system or a SoC(System-on-Chip) 2100 which is packaged and connectable to a top-sideconnector, according to some embodiments. It is pointed out that thoseelements of FIG. 10 having the same reference numbers (or names) as theelements of any other figure can operate or function in any mannersimilar to that described, but are not limited to such.

FIG. 10 illustrates a block diagram of an embodiment of a mobile devicein which flat surface interface connectors could be used. In someembodiments, computing device 2100 represents a mobile computing device,such as a computing tablet, a mobile phone or smart-phone, awireless-enabled e-reader, or other wireless mobile device. It will beunderstood that certain components are shown generally, and not allcomponents of such a device are shown in computing device 2100.

For purposes of the embodiments, the transistors in various circuits andlogic blocks described here are metal oxide semiconductor (MOS)transistors or their derivatives, where the MOS transistors includedrain, source, gate, and bulk terminals. The transistors and/or the MOStransistor derivatives also include Tri-Gate and FinFET transistors,Gate All Around Cylindrical Transistors, Tunneling FET (TFET), SquareWire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), orother devices implementing transistor functionality like carbonnanotubes or spintronic devices. MOSFET symmetrical source and drainterminals i.e., are identical terminals and are interchangeably usedhere. A TFET device, on the other hand, has asymmetric Source and Drainterminals. Those skilled in the art will appreciate that othertransistors, for example, Bi-polar junction transistors—BJT PNP/NPN,BiCMOS, CMOS, etc., may be used without departing from the scope of thedisclosure.

In some embodiments, computing device 2100 includes a first processor2110 (e.g., First die 601). The various embodiments of the presentdisclosure may also comprise a network interface within 2170 such as awireless interface so that a system embodiment may be incorporated intoa wireless device, for example, cell phone or personal digitalassistant.

In one embodiment, processor 2110 can include one or more physicaldevices, such as microprocessors, application processors,microcontrollers, programmable logic devices, or other processing means.The processing operations performed by processor 2110 include theexecution of an operating platform or operating system on whichapplications and/or device functions are executed. The processingoperations include operations related to I/O (input/output) with a humanuser or with other devices, operations related to power management,and/or operations related to connecting the computing device 2100 toanother device. The processing operations may also include operationsrelated to audio I/O and/or display I/O.

In one embodiment, computing device 2100 includes audio subsystem 2120,which represents hardware (e.g., audio hardware and audio circuits) andsoftware (e.g., drivers, codecs) components associated with providingaudio functions to the computing device. Audio functions can includespeaker and/or headphone output, as well as microphone input. Devicesfor such functions can be integrated into computing device 2100, orconnected to the computing device 2100. In one embodiment, a userinteracts with the computing device 2100 by providing audio commandsthat are received and processed by processor 2110.

Display subsystem 2130 represents hardware (e.g., display devices) andsoftware (e.g., drivers) components that provide a visual and/or tactiledisplay for a user to interact with the computing device 2100. Displaysubsystem 2130 includes display interface 2132, which includes theparticular screen or hardware device used to provide a display to auser. In one embodiment, display interface 2132 includes logic separatefrom processor 2110 to perform at least some processing related to thedisplay. In one embodiment, display subsystem 2130 includes a touchscreen (or touch pad) device that provides both output and input to auser.

I/O controller 2140 represents hardware devices and software componentsrelated to interaction with a user. I/O controller 2140 is operable tomanage hardware that is part of audio subsystem 2120 and/or displaysubsystem 2130. Additionally, I/O controller 2140 illustrates aconnection point for additional devices that connect to computing device2100 through which a user might interact with the system. For example,devices that can be attached to the computing device 2100 might includemicrophone devices, speaker or stereo systems, video systems or otherdisplay devices, keyboard or keypad devices, or other I/O devices foruse with specific applications such as card readers or other devices.

As mentioned above, I/O controller 2140 can interact with audiosubsystem 2120 and/or display subsystem 2130. For example, input througha microphone or other audio device can provide input or commands for oneor more applications or functions of the computing device 2100.Additionally, audio output can be provided instead of, or in addition todisplay output. In another example, if display subsystem 2130 includes atouch screen, the display device also acts as an input device, which canbe at least partially managed by I/O controller 2140. There can also beadditional buttons or switches on the computing device 2100 to provideI/O functions managed by I/O controller 2140.

In one embodiment, I/O controller 2140 manages devices such asaccelerometers, cameras, light sensors or other environmental sensors,or other hardware that can be included in the computing device 2100. Theinput can be part of direct user interaction, as well as providingenvironmental input to the system to influence its operations (such asfiltering for noise, adjusting displays for brightness detection,applying a flash for a camera, or other features).

In one embodiment, computing device 2100 includes power management 2150that manages battery power usage, charging of the battery, and featuresrelated to power saving operation. Memory subsystem 2160 includes memorydevices for storing information in computing device 2100. Memory caninclude nonvolatile (state does not change if power to the memory deviceis interrupted) and/or volatile (state is indeterminate if power to thememory device is interrupted) memory devices. Memory subsystem 2160 canstore application data, user data, music, photos, documents, or otherdata, as well as system data (whether long-term or temporary) related tothe execution of the applications and functions of the computing device2100.

Elements of embodiments are also provided as a machine-readable medium(e.g., memory 2160) for storing the computer-executable instructions.The machine-readable medium (e.g., memory 2160) may include, but is notlimited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs,EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM),or other types of machine-readable media suitable for storing electronicor computer-executable instructions. For example, embodiments of thedisclosure may be downloaded as a computer program (e.g., BIOS) whichmay be transferred from a remote computer (e.g., a server) to arequesting computer (e.g., a client) by way of data signals via acommunication link (e.g., a modem or network connection).

Connectivity 2170 includes hardware devices (e.g., wireless and/or wiredconnectors and communication hardware) and software components (e.g.,drivers, protocol stacks) to enable the computing device 2100 tocommunicate with external devices. The computing device 2100 could beseparate devices, such as other computing devices, wireless accesspoints or base stations, as well as peripherals such as headsets,printers, or other devices.

Connectivity 2170 can include multiple different types of connectivity.To generalize, the computing device 2100 is illustrated with cellularconnectivity 2172 and wireless connectivity 2174. Cellular connectivity2172 refers generally to cellular network connectivity provided bywireless carriers, such as provided via GSM (global system for mobilecommunications) or variations or derivatives, CDMA (code divisionmultiple access) or variations or derivatives, TDM (time divisionmultiplexing) or variations or derivatives, or other cellular servicestandards. Wireless connectivity (or wireless interface) 2174 refers towireless connectivity that is not cellular, and can include personalarea networks (such as Bluetooth, Near Field, etc.), local area networks(such as Wi-Fi), and/or wide area networks (such as WiMax), or otherwireless communication.

Peripheral connections 2180 include hardware interfaces and connectors,as well as software components (e.g., drivers, protocol stacks) to makeperipheral connections. It will be understood that the computing device2100 could both be a peripheral device (“to” 2182) to other computingdevices, as well as have peripheral devices (“from” 2184) connected toit. The computing device 2100 commonly has a “docking” connector toconnect to other computing devices for purposes such as managing (e.g.,downloading and/or uploading, changing, synchronizing) content oncomputing device 2100. Additionally, a docking connector can allowcomputing device 2100 to connect to certain peripherals that allow thecomputing device 2100 to control content output, for example, toaudiovisual or other systems.

In addition to a proprietary docking connector or other proprietaryconnection hardware, the computing device 2100 can make peripheralconnections 1680 via common or standards-based connectors. Common typescan include a Universal Serial Bus (USB) connector (which can includeany of a number of different hardware interfaces), DisplayPort includingMiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI),Firewire, or other types.

Reference in the specification to “an embodiment,” “one embodiment,”“some embodiments,” or “other embodiments” means that a particularfeature, structure, or characteristic described in connection with theembodiments is included in at least some embodiments, but notnecessarily all embodiments. The various appearances of “an embodiment,”“one embodiment,” or “some embodiments” are not necessarily allreferring to the same embodiments. If the specification states acomponent, feature, structure, or characteristic “may,” “might,” or“could” be included, that particular component, feature, structure, orcharacteristic is not required to be included. If the specification orclaim refers to “a” or “an” element, that does not mean there is onlyone of the elements. If the specification or claims refer to “anadditional” element, that does not preclude there being more than one ofthe additional element.

Furthermore, the particular features, structures, functions, orcharacteristics may be combined in any suitable manner in one or moreembodiments. For example, a first embodiment may be combined with asecond embodiment anywhere the particular features, structures,functions, or characteristics associated with the two embodiments arenot mutually exclusive

While the disclosure has been described in conjunction with specificembodiments thereof, many alternatives, modifications and variations ofsuch embodiments will be apparent to those of ordinary skill in the artin light of the foregoing description. The embodiments of the disclosureare intended to embrace all such alternatives, modifications, andvariations as to fall within the broad scope of the appended claims.

In addition, well known power/ground connections to integrated circuit(IC) chips and other components may or may not be shown within thepresented figures, for simplicity of illustration and discussion, and soas not to obscure the disclosure. Further, arrangements may be shown inblock diagram form in order to avoid obscuring the disclosure, and alsoin view of the fact that specifics with respect to implementation ofsuch block diagram arrangements are highly dependent upon the platformwithin which the present disclosure is to be implemented (i.e., suchspecifics should be well within purview of one skilled in the art).Where specific details (e.g., circuits) are set forth in order todescribe example embodiments of the disclosure, it should be apparent toone skilled in the art that the disclosure can be practiced without, orwith variation of, these specific details. The description is thus to beregarded as illustrative instead of limiting.

The following examples pertain to further embodiments. Specifics in theexamples may be used anywhere in one or more embodiments. All optionalfeatures of the apparatus described herein may also be implemented withrespect to a method or process.

For example, an apparatus is provided which comprises: a processor die;a processor substrate having a region extended away from the processordie, wherein the processor die is mounted on the processor substrate,wherein the extended region has at least one signal interface which isconnectable to a top-side connector; and an interposer coupled to theprocessor substrate and a motherboard. In some embodiments, theinterposer is extended along the direction of the extended region of theprocessor substrate. In some embodiments, the interposer is a reflowgrid array (RGA). In some embodiments, the RGA has heat traces todistribute heat uniformly in the RGA. In some embodiments, the RGA hasheat traces to evenly distribute heat to allow ball grid array (BGA)balls to reflow and attach a BGA to the RGA. In some embodiments, theprocessor substrate is a substrate of a ball grid array (BGA). In someembodiments, the top-side connector has screws to fasten the top-sideconnector to the processor substrate.

In another example, an apparatus is provided which comprises: aprocessor die; a processor substrate coupled to the processor die; andan interposer coupled to the processor substrate and a motherboard,wherein the interposer has a region which is extended away from theprocessor substrate, wherein the extended region of the interposer hasat least one signal path communicatively coupled to the processor die,and wherein the extended region of the interposer is connectable to atop-side connector. In some embodiments, the interposer is a reflow gridarray (RGA). In some embodiments, the RGA has heat traces to distributeheat uniformly in the RGA. In some embodiments, the processor substrateis a substrate of a ball grid array (BGA). In some embodiments, thetop-side connector has screws to fasten the top-side connector to theinterposer.

In another example, a system is provided which comprises: a memory; aprocessor die coupled to the memory; a package encasing the processordie, the package including: a processor substrate coupled to theprocessor die; and an interposer coupled to the processor substrate anda motherboard, wherein the interposer has a region which is extendedaway from the processor substrate, wherein the extended region of theinterposer has at least one signal path communicatively coupled to theprocessor die, and wherein the extended region of the interposer isconnectable to a top-side connector; and a wireless interface forallowing the processor to communicate with another device. In someembodiments, the interposer is a reflow grid array (RGA). In someembodiments, the RGA has heat traces to distribute heat uniformly in theRGA. In some embodiments, the processor substrate is a substrate of aball grid array (BGA). In some embodiments, the top-side connector hasscrews to fasten the top-side connector to the interposer.

In another example, a method is provided which comprises: mounting aprocessor die on to a processor substrate; mounting the processorsubstrate on to an interposer, wherein the interposer has a region whichis extended away from the processor substrate, wherein the extendedregion of the interposer has at least one signal path communicativelycoupled to the processor die, and wherein the extended region of theinterposer is connectable to a top-side connector; and coupling atop-side connector to the extended region of the interposer. In someembodiments, fastening the top-side connector to the extended region ofthe interposer with at least two screws. In some embodiments, theinterposer is a reflow grid array (RGA). In some embodiments, theprocessor substrate is a substrate of a ball grid array (BGA).

In another example, an apparatus is provided which comprises: means formounting a processor die on to a processor substrate; means for mountingthe processor substrate on to an interposer, wherein the interposer hasa region which is extended away from the processor substrate, whereinthe extended region of the interposer has at least one signal pathcommunicatively coupled to the processor die, and wherein the extendedregion of the interposer is connectable to a top-side connector; andmeans for coupling a top-side connector to the extended region of theinterposer. In some embodiments, the apparatus comprises means forfastening the top-side connector to the extended region of theinterposer with at least two screws. In some embodiments, the interposeris a reflow grid array (RGA). In some embodiments, the processorsubstrate is a substrate of a ball grid array (BGA).

An abstract is provided that will allow the reader to ascertain thenature and gist of the technical disclosure. The abstract is submittedwith the understanding that it will not be used to limit the scope ormeaning of the claims. The following claims are hereby incorporated intothe detailed description, with each claim standing on its own as aseparate embodiment.

We claim:
 1. An apparatus comprising: a processor die; a processorsubstrate having a region extended away from the processor die, whereinthe processor die is mounted on the processor substrate, wherein theextended region has at least one signal interface on the extended regionof the processor substrate, wherein the one signal interface isconfigured to be coupled to a top-side connector, wherein the one signalinterface is along a same plane as the processor die; and an interposercoupled to the processor substrate and a motherboard.
 2. The apparatusof claim 1, wherein the at least one signal interface is configured tobe coupled to a top-side connector such that the top-side connector ison a same plane as the processor die.
 3. The apparatus of claim 1,wherein the processor die is mounted on the processor substrate awayfrom the extended region of the processor substrate.
 4. The apparatus ofclaim 1, wherein the interposer is extended along the direction of theextended region of the processor substrate.
 5. The apparatus of claim 4,wherein an extended region of the interposer, along the direction of theextended region of the processor substrate, is configured to be directlyconnected to a second top-side connected via an interface on theinterposer.
 6. The apparatus of claim 4, wherein the interposercomprises a reflow grid array (RGA).
 7. The apparatus of claim 6,wherein the RGA comprises heat traces to distribute heat uniformly inthe RGA.
 8. The apparatus of claim 6, wherein the RGA comprises heattraces to evenly distribute heat to allow ball grid array (BGA) balls toreflow and attach a BGA to the RGA.
 9. The apparatus of claim 1, whereinthe processor substrate comprises a substrate of a ball grid array(BGA).
 10. The apparatus of claim 1, wherein the top-side connectorcomprises screws to fasten the top-side connector to the processorsubstrate.
 11. A system comprising: a memory; a processor die coupled tothe memory; and a package to encase the processor die, the packageincluding: a processor substrate having a region extended away from theprocessor die, wherein the processor die is mounted on the processorsubstrate, wherein the extended region has at least one signal interfaceon the extended region of the processor substrate, wherein the onesignal interface is configured to be coupled to a top-side connector,wherein the one signal interface is along a same plane as the processordie; and an interposer coupled to the processor substrate and amotherboard.
 12. The system of claim 11, wherein the at least one signalinterface is configured to be coupled to a top-side connector such thatthe top-side connector is on a same plane as the processor die.
 13. Thesystem of claim 11, wherein the processor die is mounted on theprocessor substrate away from the extended region of the processorsubstrate.
 14. The system of claim 11, wherein the interposer isextended along the direction of the extended region of the processorsubstrate.
 15. The system of claim 14, wherein an extended region of theinterposer, along the direction of the extended region of the processorsubstrate, is configured to be directly connected to a second top-sideconnector connected via an interface on the interposer.
 16. The systemof claim 14, wherein the interposer comprises a reflow grid array (RGA).17. The system of claim 16, wherein the RGA comprises heat traces todistribute heat uniformly in the RGA, wherein the RGA comprises heattraces to evenly distribute heat to allow ball grid array (BGA) balls toreflow and attach a BGA to the RGA.
 18. A method comprising: mounting aprocessor die on a processor substrate, wherein the processor substrateincludes a region extended away from the processor die, wherein theextended region has at least one signal interface on the extended regionof the processor substrate; configuring the one signal interface to becoupled to a top-side connector, wherein the one signal interface isalong a same plane as the processor die; and coupling an interposer tothe processor substrate and a motherboard.
 19. The method of claim 18,wherein configuring the at least one signal interface to be coupled to atop-side connector comprises placing the top-side connector on a sameplane as the processor die.
 20. The method of claim 18 comprising:extending the interposer along the direction of the extended region ofthe processor substrate; and configuring the interposer to be directlyconnected to a second top-side connected via an interface on theinterposer.